One of the most important characteristics of Flash EEPROM (Electrically Erasable and Programmable Read-Only Memory) devices is the program/erase cycle endurance (also called "reliability in cycling"), i.e., the number of electrical program/erase cycles to which the memory device can be submitted before a failure occurs. For next-generation Flash EEPROM devices, the manufacturers may be capable of assuring to the customers the full operability for up to 100,000 or even 1,000,000 program/erase cycles.
Flash EEPROM cells are structurally quite similar to UV EPROM cells, the only difference consisting in the gate oxide thickness: while in fact in UV EPROM cells the thickness of the gate oxide is about 200 Angstroms, Flash EEPROM cells are characterized by a gate oxide thickness of the order of 120 Angstroms. This is due to the different erasing mechanism (the mechanism by which electrons are removed from the cell's floating gate) for the two kinds of memory cells, namely electron tunneling through the gate oxide (which is therefore called "tunnel oxide") instead of UV light exposure. Since for tunneling to take place an electric field of about 10 MV/cm across the tunnel oxide is necessary, an oxide thickness of 200 Angstroms would require voltages of about 20 V, which VLSI circuits often cannot withstand; with a tunnel oxide of about 120 Angstroms, the voltages necessary to build up the required electric field drop to 11-13 V.
It has been recognized that the reliability in cycling depends on the tunnel oxide quality; this is not easy to assure, since thin oxide layers are affected by high defectivity.
A typical failure which a Flash EEPROM cell can incur when it is submitted to some thousands of program/erase cycles is the lowering of its erased-state ("1"-state) threshold voltage to negative values, which transforms the memory cell into a depletion-mode (i.e., depleted) transistor. Since a depleted memory cell always conducts a channel current even when it is not addressed, a leakage on the memory matrix bit line to which the depleted cell belongs takes place, preventing the correct reading of a programmed ("0"-state) memory cell also connected to said bit line. In-factory testing has shown that memory cells affected by this problem are randomly distributed, and after some program/erase cycles, they recover from the depleted condition.
Another typical failure which randomly affects memory cells in a Flash EEPROM device is called "gain degradation," which consists in the lowering of the "1"-state channel current of the memory cell to such a level that such cell can no longer be identified as an erased cell by the sensing circuitry of the memory device. In contrast to the above-mentioned problem, gain degradation is permanent.
Some of the memory cells subjected to gain degradation failure are characterized by anomalous erasing times: while the electrical erasure of standard memory cells requires on the average 1 s, memory cells are encountered, which after 10 ms, are almost completely erased; such memory cells are called "fast erase bits". Differently from what could be expected, at the end of the erasing procedure, such memory cells achieve a very low threshold voltage, but are not depleted. This feature characterizes the fast erase bits with respect to those memory cells affected by depletion failure: also these fast erase bits are in fact erased faster than the average memory cell, but there is no lower limit to their threshold voltage, which can become negative.
The mechanism at the basis of the fast-erase-bit behavior has not been univocally determined yet. Two explanations have been proposed: one assumes that a localized thinning of the tunnel oxide takes place, causing a localized increase in the electric field; electron tunneling occurs in the region where the electric field is higher, and the erasing time, which depends exponentially on the electric field, is therefore greatly reduced. Another possible explanation is the existence of energy levels, introduced by charge traps within the tunnel oxide, which reduces the energy gap between the conduction and valence energy bands of the oxide; this defect could be activated after a given number of program/erase cycles.